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Nvidia Vera uses a coherency fabric to feed high-core-count server CPUs

chipsandcheese.com by Chester Lam 8 min read Editor score 8/10

Vera's second-generation Scalable Coherency Fabric connects cores, cache and off-chip I/O; its coherency switch nodes host pairs of cores to keep node count under control. The design details help engineers reason about bandwidth and interconnect trade-offs in server chips.

What
Vera pairs high-throughput Olympus cores with Nvidia’s second-generation Scalable Coherency Fabric (SCF).
How
Coherency Switch Nodes connect cores and cache; Memory Switch Nodes bridge to LPDDR5X controllers, while Bridge Switch Nodes host PCIe controllers.
Why it matters
Reported low latency under bandwidth load could help Vera control noisy-neighbor effects and scale in DRAM-bound workloads.
memory traffic memory access I/O traffic peripheral I/O Coherency SwitchNodes Memory SwitchNodes Bridge SwitchNodes LPDDR5X memorycontrollers PCIe controllers
SCF switch nodes connect Vera’s cores and cache to memory and peripheral controllers. Sketched from the article's own text.

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