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SpyreCode turns KTIR kernels into double-buffered dataflow schedules

pytorch.org 30 min read Editor score 8/10

A new MLIR scheduler converts KTIR into dataflow pipelines, routing transfers through the hardware memory hierarchy and expanding schedules into nested, double-buffered instances. The compiler design shows how accelerator backends can map tiled kernels to distributed scratchpad memory.

What
The Spyre backend compiler converts KTIR kernel mappings into schedules and code for IBM Spyre.
How
Dataflow Scheduler splits tiles into programs, routes transfers through the memory hierarchy, and expands pipelines into double-buffered schedules.
Why it matters
KTIR carries Inductor's mapping decisions forward, producing artifacts that the Spyre runtime can prepare and launch.
kernel mapping schedule lowering artifact KTIR DataflowScheduler DataflowIR SpyreCode Spyre runtime
The compiler pipeline transforms KTIR mappings into a launchable Spyre artifact. Sketched from the article's own text.

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